Cornelis Networks, Inc.: PCIe ASIC Design Engineer

Overview

Cornelis Networks, Inc. is at the forefront of delivering high-performance scale-out networking solutions tailored for Artificial Intelligence (AI) and High-Performance Computing (HPC) datacenters. The company prides itself on its innovative architecture that seamlessly integrates hardware, software, and system-level technologies. This integration maximizes the efficiency of GPU, CPU, and accelerator-based compute clusters, enabling clients to push the limits of innovation. With support from top-tier venture capital and strategic investors, Cornelis Networks is dedicated to addressing the world’s most demanding computational challenges through their next-generation networking solutions.

Company Culture

As a fast-growing organization, Cornelis Networks boasts a dynamic team of architects, engineers, and business professionals with a proven history of launching successful products and companies. Their global workforce spans several U.S. states and six countries, allowing for a diverse workplace culture. They focus on innovation, performance, and scalability, constantly looking for exceptional talent for both onsite and remote roles.

Position and Role

Cornelis Networks is currently looking for a Senior ASIC Design Engineer whose primary responsibility will be leading the design and integration of PCIe controllers into next-generation System on Chips (SoCs). This role involves extensive knowledge of the PCI Express protocol across multiple generations, including Gen4, Gen5, and Gen6. The ideal candidate will be instrumental in driving performance optimization and ensuring seamless integration of PCIe IP into complex ASIC designs.

Key Responsibilities

The key responsibilities for this position include:

Taking ownership of the end-to-end integration of PCIe IP into complex ASIC designs.
Collaborating with IP vendors, architecture teams, verification personnel, and software teams to produce robust PCIe subsystems.
Spearheading performance optimization efforts related to the entire PCIe stack, including tuning PHY and improving DMA/transaction layer efficiency.
Engaging in system architecture and microarchitecture discussions with an emphasis on IO and interconnect scalability.
Taking the lead on silicon bring-up and validation of PCIe links in laboratory settings, working closely with board and firmware teams.
Debugging functional and performance issues at RTL, gate-level, and silicon stages.
Ensuring compliance with PCIe specifications and engaging in necessary interoperability testing.
Mentoring junior engineers and contributing to the establishment of best practices in PCIe subsystem development.

Qualifications

To excel in this role, candidates must meet certain qualifications:

Minimum Qualifications:

A BS/MS degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of industry experience in ASIC/SoC design, specifically focusing on PCIe controller integration.
Proven success in the silicon bring-up of high-speed interfaces and an in-depth understanding of the PCIe protocol stack, including PHY, MAC, TLP, and DLL.
Hands-on experience with PCIe verification environments, performance tuning, and power-aware design methodologies.
Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and laboratory equipment like protocol analyzers and oscilloscopes.
Strong scripting skills in Python, Perl, or TCL and excellent debugging capabilities.
Strong verbal and written communication skills are essential.

Preferred Qualifications:

Candidates with the following skills and experiences will be given preference:

Experience with PCIe Gen5/Gen6 and advanced solutions such as retimers or switches.
Exposure to CXL, CCIX, or other cache-coherent interconnects and familiarity with data center or AI/ML accelerator architectures.
Experience working with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) dedicated to PCIe subsystem validation.

Compensation and Benefits

Cornelis Networks provides a competitive compensation package that includes both equity and cash along with various health and retirement benefits. The company's payment structure considers various factors, such as skills, qualifications, experience, and geographic location, ensuring a fair compensation relative to market standards. Depending on the role, candidates may qualify for performance-based incentives, including annual bonuses or sales incentives.

In addition to base salaries, employees enjoy a comprehensive range of benefits, including:

Medical, dental, and vision coverage.
Disability and life insurance.
A dependent care flexible spending account.
Accidental injury insurance and pet insurance.
Generous paid holiday schedules.
401(k) plans with company matching.
Open Time Off (OTO) for regular full-time exempt employees, along with paid sick time, bonding leave, and pregnancy disability leave.

Application Process

For skilled professionals eager to join an innovative and forward-thinking company, applying to Cornelis Networks offers a fantastic opportunity. As an equal opportunity employer, Cornelis Networks welcomes applicants from all backgrounds and will accommodate needs throughout the recruitment process.

In summary, the Senior ASIC Design Engineer role at Cornelis Networks presents an exciting pathway for career growth in the rapidly evolving field of networking technology. The opportunity to develop cutting-edge solutions and contribute to shaping the future of AI and HPC datacenters is both lucrative and rewarding.

This job offer was originally published on weworkremotely.com